1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device comprising a bipolar transistor having an insulating gate and a method of manufacturing the semiconductor device.
2. Description of the Background Art
In power electronics for driving a motor or the like, an IGBT (Insulated Gate Bipolar Transistor) has mainly been used as a switching element based on a characteristic in a region in which a rated voltage is 300 V or more.
FIG. 27 is a sectional view showing a structure of a conventional trench gate type IGBT (TIGBT). As shown in FIG. 27, an N+ buffer layer 32 is formed on a P+ substrate 31 and an Nxe2x88x92 layer 33 is formed on the N+ buffer layer 32.
A P base region 35 is selectively formed on the Nxe2x88x92 buffer layer 33, and furthermore, an N+ emitter region 36 is selectively formed in a surface of the P base region 35. The P base region 35 can be formed by diffusing a P-type impurity and the N+ emitter region 36 can be formed by diffusing an N-type impurity having a high concentration.
A trench 37 is formed to reach the upper layer portion of the Nxe2x88x92 layer 33 adjacently to the N+ emitter region 36 through the P base region 35, and a gate electrode 39 is buried in the trench 37 through a gate insulating film 38 formed on an internal wall of the trench 37. The gate electrode 39 is formed of polysilicon.
A region of the P base region 35 opposed to the gate electrode 39 through the gate insulating film 38 is defined as a channel region. An interlayer insulating film 40 is formed over a large part of a surface of the N+ emitter region 36 and the gate insulating film 38, an emitter electrode 42 is formed over a part of the surface of the N+ emitter region 36 (a portion excluding the large part) and a surface of the P base region 35, and a collector electrode 43 is formed on a back face of the P+ substrate 31.
FIG. 28 is a sectional view showing a structure of a carrier stored TIGBT (CSTBT; Carrier Stored Trench-gate Bipolar Transistor devised by the inventors. As shown in FIG. 28, the TIGBT is different from the TIGBT shown in FIG. 27 in that an N layer 34 is formed between the Nxe2x88x92 layer 33 and the P base region 35. The N layer 34 is provided for storing a carrier in a region which is shallower than a bottom portion of the trench 37.
Next, the operation of the IGBTs (TIGBT and CSTBT) shown in FIGS. 27 and 28 will be described.
In the structures shown in FIGS. 27 and 28, when a predetermined collector voltage VCE is set between the emitter electrode 42 and the collector electrode 43 and a predetermined gate voltage VGE to bring an ON state is applied between the emitter electrode 42 and the gate electrode 39, a channel region in the P base region 35 is inverted to have an N type so that a channel is formed.
An electron is injected from the emitter electrode 42 into the Nxe2x88x92 layer 33 (N layer 34) through the channel. By the electron thus injected, a forward bias is applied between the P+ substrate 31 and the Nxe2x88x92 layer 33 (N+ buffer layer 32), a hole is injected from the P+ substrate 31, a resistance value of the Nxe2x88x92 layer 33 is considerably reduced and a current capacity of the IGBT is enhanced. Thus, the IGBT can reduce the resistance value of the Nxe2x88x92 layer 33 by the injection of the hole from the P+ substrate 31.
Next, an operation of the IGBT from an ON state to an OFF state will be described. In the structures shown in FIGS. 27 and 28, the gate voltage VGE applied in the ON state between the emitter electrode 42 and the gate electrode 39 is changed into an OFF state such that xe2x80x9c0xe2x80x9d or a backward bias is applied.
Consequently, the channel region inverted to the N type is returned to the P type so that the injection of the electron from the emitter region 42 is also stopped. By the stop of the injection of the electron, the injection of the hole from the P+ substrate 31 is also stopped. Then, the electron and the hole which are stored in the Nxe2x88x92 layer 33 (N+ buffer layer 32) go through the collector electrode 43 and the emitter electrode 42 respectively or are recombined with each other and are annihilated.
In the case of the TIGBT shown in FIG. 27, a MOS structure of the surface is reduced to approximately {fraction (1/10)} as compared with a plane gate type IGBT. Therefore, a characteristic can be enhanced. Moreover, a current flows to an N region interposed between the P base regions of the adjacent cells over the surface in the plane gate type IGBT. In this region, a voltage drop is great.
However, the gate electrode 39 is formed in a direction of a depth through the P base region 35 in the TIGBT. Consequently, the Nxe2x88x92 layer 33 interposed between the P base regions 35 is not present in a current path. Therefore, an operation characteristic can be enhanced.
In the CSTBT shown in FIG. 28, the N layer 34 is formed under the P base region 35. Therefore, the hole sent from the P+ substrate 31 can be prevented from reaching the emitter electrode 42. Consequently, the hole is stored under the P base region 35 and an ON-state voltage can be more reduced than that in the TIGBT.
An IGBT having a trench gate structure shrinks to {fraction (1/10)} or more as compared with the plane gate type so that the number of gates is increased. Therefore, there is a problem in that a gate capacity is increased. In order to solve the problem, there has been a method of increasing a cell size to reduce the number of gates. If this method is employed, however, the ON-state voltage is raised in the TIGBT and the ON-state voltage is less raised and a breakdown voltage is dropped in the CSTBT. Therefore, the problem cannot be solved practically.
FIG. 29 is a graph showing a relationship between a trench space between the adjacent trenches (a distance between the trenches and a distance between opposed trench ends) and an ON-state voltage in each of the TIGBT and CSTBT. FIG. 30 is a graph showing a relationship between the trench space and a breakdown voltage in each of the TIGBT and the CSTBT. In FIGS. 29 and 30, a curve LT indicates the characteristic of the TIGBT and a curve LC indicates the characteristic of the CSTBT.
Conventionally, the trench space in each of the TIGBT and the CSTBT has been designed to 3 xcexcm. In FIGS. 29 and 30, the trench space is equal to or less than approximately 11 xcexcm. If the trench space is 11 xcexcm, a cell size is increased to three times as large as that in the conventional art and a gate capacity is reduced to ⅓.
In FIG. 29, the ON-state voltage is not greatly changed even if the trench space is increased in the CSTBT as shown in the curve LC, while the ON-state voltage is raised to such a level as not to be negligible with an increase in the trench space in the TIGBT as shown in the curve LT.
In FIG. 30, the breakdown voltage of the TIGBT is less dropped even if the trench space is increased as shown in the curve LT, while the breakdown voltage is rapidly dropped with an increase in the trench space in the CSTBT as shown in the curve LC, and particularly, approximates to 0 V if the trench space exceeds 5 xcexcm.
In the conventional TIGBT and CSTBT, thus, the ON-state voltage is raised or the breakdown voltage is dropped. Therefore, there is a problem in that the trench space to reduce the gate capacity cannot be increased.
In common to the IGBTs (TIGBT and CSTBT), moreover, there is a problem in that a parasitic bipolar transistor (BIP-Tr) formed by the Nxe2x88x92 layer 33 (the N layer 34 in the CSTBT shown in FIG. 28), the P base region 35 and the N+ emitter region 36 is present.
When the parasitic BIP-Tr is operated, the IGBT cannot be controlled and is broken down. Since the CSTBT forms the N layer 34, a resistance value in the vicinity of the P base region 35 is greater than that in the TIGBT and the parasitic BIP-Tr is operated more easily than that in the TIGBT.
Moreover, Japanese Patent Application Laid-Open No. 9-331063 (1997) has proposed some structures to solve the problems of the TIGBT.
FIG. 31 is a sectional view showing a first improved structure of the TIGBT. As shown in FIG. 31, an N+ buffer layer 102, an Nxe2x88x92 layer 101 and a P base region 104 are formed on a P+ substrate 103, an N+ emitter region 105 is selectively formed on a surface of the P base region 104, and a gate trench 70 is formed from a surface of the N+ emitter region 105 to the Nxe2x88x92 layer 101 through the N+ emitter region 105 and the P base region 104. The gate trench 70 includes a gate insulating film 107 and a gate electrode 108 which are formed in a gate trench 107A.
The gate electrode 108 has side and upper surfaces covered with an insulating film 118, a silicate glass film 119 is further formed on the gate electrode 108 through the insulating film 118, and a CVD oxide film 120 is formed on a part of the silicate glass film 119.
Moreover, an emitter trench 80 is formed between the gate trenches 70 and 70 to reach the Nxe2x88x92 layer 101 through the P base region 104 from the surface of the P base region 104 on which the N+ emitter region 105 is not formed. The emitter trench 80 includes an emitter insulating film 80b and an emitter trench electrode 80c which are formed in an emitter trench 80a. 
An emitter electrode 110 is formed on a part of the N+ emitter region 105 and the P base region 104 so as to be electrically connected to a part of the emitter trench electrode 80c through a contact hole 50 formed in the silicate glass film 119, and a collector electrode 111 is formed on a back face of the P+ substrate 103.
Such a first improved structure is different from the TIGBT shown in FIG. 27 in that the emitter trench 80 is provided between the gate trenches 70 and 70. With this structure, a gate capacity can be equal to that of the TIGBT shown in FIG. 27 by setting a trench space between the gate trenches 70 and 70 functioning as gate electrodes to be almost equal to that of the TIGBT shown in FIG. 27.
With the first improved structure, the emitter trench 80 is further formed between the gate trenches 70 and 70. Therefore, a trench space dx (a residual width of silicon) between the gate trench 70 and the emitter trench 80 which are adjacent to each other is 0.2 xcexcm. Thus, there has been disclosed a technique which is very hard to implement in the current manufacturing technology.
FIG. 32 is a sectional view showing a second improved structure of the TIGBT. As shown in FIG. 32, a plurality of emitter trenches 80 are formed between the gate trenches 70 and 70. The emitter trench 80 has the emitter trench electrode 80c formed in the emitter insulating film 80b. 
A silicate glass film 110A is formed over the whole surface of a P base region 104 between the emitter trenches 80 and 80. An emitter electrode 110 is formed over the whole surface and is directly formed on a part of an N+ emitter layer 105, the P base region 104 adjacent to the gate trench 70 and the emitter trench electrode 80c. Other structures are the same as those of the first improved structure shown in FIG. 31.
In the second improved structure, the emitter trenches 80 are provided between the gate trenches 70 and 70 so that a trench space between the gate trenches 70 and 70 can be increased. Consequently, a gate capacity can be increased.
However, a hole injected from the collector electrode 111 to the P+ substrate 103 reaches the P base region 104 electrically connected to the emitter electrode 110, that is, the emitter electrode 110 through only the P base region 104 adjacent to the gate trench 70.
For this reason, a collector saturation voltage VCE (sat) is not simply raised differently from the structure of the TIGBT in FIG. 27 in which the P base region 35 is expanded over almost the whole surface but the hole can be stored in the P base region 104 which is not electrically connected to the emitter electrode 110, that is, a portion provided under the P base region 104 between the emitter trenches 80 and 80. Consequently, the ON-state voltage can be reduced.
The presence of the P base region 104 which is not electrically connected to the emitter electrode 110 has the following problems. In an OFF process of the IGBT, the hole is to reach the emitter electrode 110. However, a large part of the P base region 104 is not electrically connected to the emitter electrode 110. Therefore, the hole cannot sufficiently reach the emitter electrode 110. Thus, there is a problem in that an OFF operation of the IGBT is adversely influenced. In the OFF process, moreover, the hole reaching the emitter electrode 110 passes through the P base region 104 which is electrically connected to the emitter electrode 110. Therefore, there is a problem in that the parasitic BIP-Tr can be operated more easily than in the TIGBT shown in FIG. 27.
A first aspect of the present invention is directed to a semiconductor device comprising a first semiconductor layer of a first conductivity type having first and second major surface, a second semiconductor layer of a second conductivity type formed on the first major surface of the first semiconductor layer, a third semiconductor layer of the second conductivity type formed on the second semiconductor layer, a fourth semiconductor layer of the first conductivity type formed on the third semiconductor layer, a first trench and at least one second trench arranged to penetrate through at least the fourth semiconductor layer from a surface of the fourth semiconductor layer, a first semiconductor region of the second conductivity type selectively formed in the surface of the fourth semiconductor layer adjacently to the first trench, a first insulating film formed on an internal wall of the first trench, a control electrode buried in the first trench through the first insulating film, the control electrode being not formed in the at least one second trench, a first main electrode electrically connected to at least a part of the first semiconductor region and formed over an almost whole surface of the fourth semiconductor layer, and a second main electrode formed on the second major surface of the first semiconductor layer.
A second aspect of the present invention is directed to the semiconductor device according to the first aspect of the present invention, wherein a distance between the first trench and the at least one second trench is set to 5 xcexcm or less.
A third aspect of the present invention is directed to the semiconductor device according to the first aspect of the present invention, wherein the first trench includes a trench formed in a predetermined direction seen on a plane, the at least one second trench includes a trench formed in the predetermined direction seen on a plane, the first semiconductor region includes a first partial region formed in the vicinity of the first trench and a second partial region extended from the first partial region in such a direction as to go away from the first trench, and the first main electrode is directly formed on the second partial region to carry out electrical connection to the first semiconductor region.
A fourth aspect of the present invention is directed to the semiconductor device according to the third aspect of the present invention, wherein the first semiconductor region includes a third partial region which is further extended from the second partial region and is formed in the vicinity of the at least one second trench, and the first main electrode is further formed directly on the third partial region to carry out electrical connection to the first semiconductor region.
A fifth aspect of the present invention is directed to the semiconductor device according to the fourth aspect of the present invention, wherein the second and third partial regions include a plurality of second and third partial regions respectively, and the plurality of third partial regions are selectively formed in the vicinity of the at least one second trench.
A sixth aspect of the present invention is directed to the semiconductor device according to any of the first to fifth aspects of the present invention, further comprising a second semiconductor region of the first conductivity type formed in the surface of the fourth semiconductor layer adjacently to the at least one second trench, the second semiconductor region having a concentration of an impurity of the first conductivity type set to be higher than that of the fourth semiconductor layer.
A seventh aspect of the present invention is directed to the semiconductor device according to the sixth aspect of the present invention, wherein the concentration of the impurity of the first conductivity type in the second semiconductor region is set to be higher than a concentration of an impurity of the second conductivity type in the first semiconductor region.
An eighth aspect of the present invention is directed to the semiconductor device according to any of the first to seventh aspects of the present invention, wherein the at least one second trench includes a plurality of second trenches.
A ninth aspect of the present invention is directed to the semiconductor device according to any of the first to seventh aspects of the present invention, wherein the first trench and the at least one second trench have equal formation depths.
A tenth aspect of the present invention is directed to the semiconductor device according to any of the first to seventh aspects of the present invention, wherein the first trench and the at least one second trench have equal formation widths.
An eleventh aspect of the present invention is directed to the semiconductor device according to any of the first to seventh aspects of the present invention, further comprising a second insulating film formed on an internal wall of the at least one second trench.
A twelfth aspect of the present invention is directed to the semiconductor device according to the eleventh aspect of the present invention, further comprising is a conductive region buried in the at least one second trench through the second insulating film.
A thirteenth aspect of the present invention is directed to the semiconductor device according to the twelfth aspect of the present invention, wherein the first main electrode is directly formed on the conductive region.
A fourteenth aspect of the present invention is directed to the semiconductor device according to any of the first to thirteenth aspects of the present invention, further comprising a sixth semiconductor layer of the second conductivity type formed between the first semiconductor layer and the second semiconductor layer, the sixth semiconductor layer having a concentration of an impurity of the second conductivity type set to be higher than that of the second semiconductor layer.
A fifteenth aspect of the present invention is directed to a method of manufacturing a semiconductor device, comprising the steps of (a) preparing a substrate including a first semiconductor layer of a first conductivity type having first and second major surfaces and a second semiconductor layer of a second conductivity type formed on the first main surface of the first semiconductor layer, (b) forming a third semiconductor layer of the second conductivity type on the second semiconductor layer, (c) forming a fourth semiconductor layer of the first conductivity type on the third semiconductor layer, (d) selectively forming a first semiconductor region of the second conductivity type in a surface of the fourth semiconductor layer, (e) selectively forming a first trench to penetrate through at least the first semiconductor region and the fourth semiconductor layer from the surface of the fourth semiconductor layer, (f) forming a first insulating film on an internal wall of the first trench, (g) burying a control electrode in the first trench through the first insulating film, (h) forming at least one second trench adjacently to and apart from the first trench to penetrate through at least the fourth semiconductor layer from the surface of the fourth semiconductor layer, (i) forming a first main electrode electrically connected to at least a part of the first semiconductor region over an almost whole surface of the fourth semiconductor layer, and (j) forming a second main electrode on the second major surface of the first semiconductor layer.
A sixteenth aspect of the present invention is directed to the method of manufacturing a semiconductor device according to the fifteenth aspect of the present invention, wherein the steps (e) and (h) are executed such that a distance between the first trench and the at least one second trench is set to 5 xcexcm or less.
A seventeenth aspect of the present invention is directed to the method of manufacturing a semiconductor device according to the fifteenth aspect of the present invention, wherein the step (e) includes the step of forming the first trench in a predetermined direction seen on a plane, the step (h) includes the step of forming the at least one second trench in the predetermined direction seen on a plane, after the steps (d) and (e) are executed, the first semiconductor region includes a first partial region formed in the vicinity of the first trench and a second partial region extended from the first partial region in such a direction as to go away from the first trench, and the step (i) includes the step of directly forming the first main electrode on the second partial region.
An eighteenth aspect of the present invention is directed to the method of manufacturing a semiconductor device according to the fifteenth or sixteenth aspect of the present invention, further comprising the step of (k) forming a second semiconductor region of the first conductivity type in the surface of the fourth semiconductor layer, the second semiconductor region having a concentration of an impurity of the first conductivity type set to be higher than the fourth semiconductor layer.
A nineteenth aspect of the present invention is directed to the method of manufacturing a semiconductor device according to any of the fifteenth to eighteenth aspects of the present invention, wherein the step (e) and the step (h) are executed simultaneously.
A twentieth aspect of the present invention is directed to the method of manufacturing a semiconductor device according to any of the fifteenth to eighteenth aspects of the present invention, further comprising the step of (l) forming a second insulating film  less than 14 greater than on an internal wall of the at least one second trench, the step (f) and the step (l) being executed simultaneously.
A twenty-first aspect of the present invention is directed to the method of manufacturing a semiconductor device according to the twentieth aspect of the present invention, further comprising the step of (m) burying a conductive region in the at least one second trench through the second insulating film, the step (g) and the step (m) being executed simultaneously.
A twenty-second aspect of the present invention is directed to the method of manufacturing a semiconductor device according to any of the fifteenth to twenty-first aspects of the present invention, the step (a) including the steps of (a-1) preparing the first semiconductor layer, and (a-2) forming the second semiconductor layer over the first main surface of the first semiconductor layer by epitaxial growth.
A twenty-third aspect of the present invention is directed to the method of manufacturing a semiconductor device according to any of the fifteenth to twenty-first aspects of the present invention, the step (a) including the steps of (a-1) preparing the second semiconductor layer, and (a-2) implanting an impurity of the first conductivity type from a back face of the second semiconductor layer, thereby forming the first semiconductor layer in a lower layer portion of the second semiconductor layer.
As described above, according to the first aspect of the present invention, the first trench having the control electrode provided therein and at least one second trench having no control electrode provided therein are formed together. Therefore, it is possible to reduce a capacity attended with the control electrode.
In this case, the distance between the first trench and at least one second trench is set such that a sufficient breakdown voltage can be maintained. Consequently, it is also possible to sufficiently prevent a reduction in the breakdown voltage. In addition, it is also possible to sufficiently prevent an ON-state voltage from being raised by the presence of the third semiconductor layer.
Furthermore, the first main electrode is formed over the almost whole surface of the fourth semiconductor layer. Therefore, a carrier can be caused to well flow between the fourth semiconductor layer and the first main electrode so that an operation characteristic can be enhanced.
As a result, the semiconductor device according to the first aspect of the present invention can minimize an increase in the capacity attended with the control electrode without adversely influencing the operation characteristic including the ON-state voltage, the breakdown voltage and the like.
According to the second aspect of the present invention, the distance between the first trench and at least one second trench is set to 5 xcexcm or less. Consequently, a sufficient breakdown voltage can be maintained.
According to the third aspect of the present invention, the first main electrode is directly formed on the second partial region to carry out the electrical connection to the first semiconductor region. Therefore, it is possible to effectively prevent a parasitic bipolar transistor comprising the first semiconductor region, the fourth semiconductor layer and the third semiconductor layer from being operated.
According to the fourth aspect of the present invention, the first main electrode is further formed directly on the third partial region to carry out the electrical connection. Consequently, it is possible to more reduce a contact resistance of the first main electrode and the first semiconductor region.
According to the fifth aspect of the present invention, a plurality of third partial regions are selectively formed in the vicinity of at least one second trench. Therefore, it is possible to balance the prevention of the operation of the parasitic bipolar transistor with the reduction in the contact resistance.
According to the sixth aspect of the present invention, the contact resistance between the fourth semiconductor layer and the first main electrode can be reduced by the second semiconductor region having the higher concentration of the impurity of the first conductivity type than that of the fourth semiconductor layer. Therefore, it is possible to suppress the operation of the parasitic bipolar transistor.
According to the seventh aspect of the present invention, the concentration of the impurity of the first conductivity type in the second semiconductor region is set to be higher than the concentration of the impurity of the second conductivity type in the first semiconductor region. Therefore, it is possible to suppress the degree of diffusion during the formation of the first semiconductor region. Correspondingly, the device can be microfabricated.
According to the eighth aspect of the present invention, a plurality of second trenches are arranged for one first trench. Therefore, the arrangement is formed repetitively so that the plurality of second trenches can be provided between two first trenches. Thus, it is possible to increase a design margin on the distance between the first trenches.
According to the ninth aspect of the present invention, the first trench and at least one second trench are set to have equal formation depths. Consequently, it is possible to increase a design margin related to the breakdown voltage.
According to the tenth aspect of the present invention, the first trench and at least one second trench are set to have equal formation widths. Consequently, when the first trench and at least one second trench are to be formed simultaneously, they can easily be formed with equal depths.
According to the eleventh aspect of the present invention, the second insulating film is formed on the internal wall of at least one second trench. Therefore, if the first and second insulating films are formed simultaneously, the first and second insulating films can be formed efficiently on the internal walls of the first trench and at least one second trench, respectively.
According to the twelfth aspect of the present invention, the conductive region is further buried in at least one second trench through the second insulating film. Therefore, if the control electrode and the conductive region are simultaneously formed of the same material, the control electrode and the conductive region can be formed efficiently in the first trench and at least one second trench, respectively.
According to the thirteenth aspect of the present invention, the first main electrode is directly formed on the conductive region. Therefore, it is not necessary to consider a margin on the electrode region, the insulating film covering the vicinity thereof and the like. Consequently, it is possible to reduce the distance between the first trench and at least one second trench.
According to the fourteenth aspect of the present invention, the second semiconductor layer can be formed with a small thickness by the presence of the sixth semiconductor layer having the higher concentration of the impurity of the second conductivity type than that of the second semiconductor layer. Consequently, it is possible to enhance an operation characteristic such as a reduction in an ON-state voltage.
In the semiconductor device manufactured by the method of manufacturing a semiconductor device according to the fifteenth aspect of the present invention, the first trench having the control electrode provided therein and at least one second trench having no control electrode provided therein are formed together. Therefore, it is possible to reduce a capacity attended with the control electrode.
In this case, the steps (e) and (h) are executed such that the distance between the first trench and at least one second trench can maintain a sufficient breakdown voltage. Consequently, it is also possible to sufficiently prevent a reduction in the breakdown voltage. In addition, it is also possible to sufficiently prevent an ON-state voltage from being raised by the presence of the third semiconductor layer formed at the step (c).
At the step (i), furthermore, the first main electrode is formed over the almost whole surface of the fourth semiconductor layer. Therefore, a carrier can be caused to well flow between the fourth semiconductor layer and the first main electrode so that an operation characteristic can be enhanced.
As a result, in the method of manufacturing a semiconductor device according to the fifteenth aspect of the present invention, it is possible to manufacture a semiconductor device capable of minimizing an increase in the capacity attended with the control electrode without adversely influencing the operation characteristic including the ON-state voltage, the breakdown voltage and the like.
In the semiconductor device manufactured by the method of manufacturing a semiconductor device according to the sixteenth aspect of the present invention, the distance between the first trench and at least one second trench is set to 5 xcexcm or less. Consequently, a sufficient breakdown voltage can be maintained.
According to the seventeenth aspect of the present invention, at the step (i), the first main electrode is directly formed on the second partial region to carry out the electrical connection of the first main electrode and the first semiconductor region. By the presence of the second partial region of the first semiconductor region, therefore, it is possible to effectively prevent a parasitic bipolar transistor comprising the first semiconductor region, the fourth semiconductor layer and the third semiconductor layer from being operated.
According to the eighteenth aspect of the present invention, at the step (k), the second semiconductor region of the first conductivity type which has the higher concentration of the impurity of the first conductivity type than that of the fourth semiconductor layer is formed in the surface of the fourth semiconductor layer.
Accordingly, it is possible to reduce a contact resistance between the fourth semiconductor layer and the first main electrode by the second semiconductor region. Consequently, it is possible to suppress the operation of the parasitic bipolar transistor.
According to the nineteenth aspect of the present invention, the steps (e) and (h) are executed simultaneously. Consequently, it is possible to efficiently form the first trench and at least one second trench.
According to the twentieth aspect of the present invention, the steps (f) and (l) are executed simultaneously. Consequently, it is possible to efficiently form the first and second insulating films on the internal walls of the first trench and at least one second trench.
According to the twenty-first aspect of the present invention, the steps (g) and (m) are executed simultaneously. Consequently, it is possible to efficiently form the control electrode and the conductive region in the first trench and at least one second trench.
According to the twenty-second aspect of the present invention, at the step (a-2), the second semiconductor layer is formed by the epitaxial growth. Therefore, it is possible to form the second semiconductor layer with good controllability of the concentration of the impurity and a film thickness.
According to the twenty-third aspect of the present invention, at the step (a2), the impurity of the first conductivity type is implanted from the back face of the second semiconductor layer to form the first semiconductor layer. Therefore, it is possible to manufacture the semiconductor device comparatively inexpensively.
In order to solve the above-mentioned problems, it is an object of the present invention to provide a semiconductor device in which an increase in a gate capacity can be minimized without adversely influencing an operation characteristic and a method of manufacturing the semiconductor device.